1. Field of the Invention
The present invention relates to a semiconductor device and a process for producing the same and, more particularly, to a semiconductor device comprising an SRAM cell having TFTs as load transistors, and a process for producing the same.
2. Description of the Prior Art
A conventional SRAM cell having thin film transistors (TFTs) as PMOS load transistors will be hereinafter described. FIG. 11 shows an equivalent circuit of the SRAM cell having PMOS load transistors. The SRAM cell comprises a flip-flop circuit and access transistors ATr1 and ATr2. The flip-flop circuit includes drive transistors DTr1 and DTr2 formed on a semiconductor substrate and MOS load TFTs TFT1 and TFT2 stacked on the drive transistors DTr1 and DTr2 for receiving power supply at the nodes thereof. The access transistors ATr1 and ATr2 are connected by nodes thereof to corresponding bit lines BL, respectively. Such construction as having the MOS load thin film transistors TFT1 and TFT2 stacked on the respective drive transistors DTr1 and DTr2 on the semiconductor substrate makes it possible to reduce the size of each SRAM cell and hence to increase the memory capacity of the whole SRAM.
With reference to FIGS. 24 to 32, a conventional process for producing a TFT in the aforesaid SRAM will be described below.
A field isolation film 71 is formed on a silicon substrate 70 for device isolation. Then, drive MOS transistors DTr1 and DTr2 are formed on the silicon substrate 70 in a known manner. An interlayer insulation film 72 is formed over the entire surface of the silicon substrate 70, and then a contact hole 72a is formed in the interlayer insulating film 72 above a desired region, i.e., above a region where a gate electrode 73 of the drive transistor DTr2 and a source/drain region 74 of the drive transistor DTr1 are formed, as shown in FIG. 24.
In turn, as shown in FIG. 25, a polysilicon film is deposited over the entire surface of the silicon substrate 70 including the contact hole 72a, and then patterned into a desired configuration to form a gate electrode 75a of a TFT and polysilicon pads 75b and 75c which serve as semiconductor pads for the wiring of the TFT. The polysilicon film has a thickness of about 100 nm to about 200 nm, and is doped with such an N-type impurity as phosphorus or arsenic ions in a high concentration of about 10.sup.20 cm.sup.-3 or more. The doping of the polysilicon film with the N-type impurity may be achieved by ion-implanting or diffusing the impurity into polysilicon which has been deposited on the substrate by way of low pressure CVD, or by depositing doped silicon on the substrate using phosphine (PH.sub.3) gas and silane (SiH.sub.4) gas. The provision of the polysilicon pad 75b enables the gate electrode 73 of the drive transistor DTr2 to be connected to the source/drain region 74 of the drive transistor DTr1 and at the same time to either of source/drain regions of the TFT 1 which are to be formed in a later process, at a connection point A shown in FIG. 11. Though the TFT 1 and the drive transistors DTr1 and DTr2 are connected at the same time in this case, the contact hole 72a may be formed only on the gate electrode 73 of the drive transistor DTr2 or only on the source/drain region 74 of the drive transistor DTr1. In such a case, however, the gate electrode 73 of the drive transistor DTr2 and the source/drain region 74 of the drive transistor DTr1 should be connected by any means other than the contact hole 72a.
Subsequently, as shown in FIG. 26, an SiO.sub.2 film with a thickness of about 10 nm to about 50 nm is deposited on the entire surface of the silicon substrate 70 including the gate electrode 75a of the TFT and polysilicon pads 75b and 75c by way of CVD to form a gate oxide film 76 of the TFT.
Then, as shown in FIG. 27, openings 76a are formed in the gate oxide film 76 above the polysilicon pads 75b and 75c by photolithography and RIE process.
In turn, as shown in FIG. 28, a polysilicon film with a thickness of about 10 nm to about 100 nm is deposited on the entire surface of the silicon substrate 70 including the openings 76a by way of low pressure CVD, and then patterned into a desired configuration to form an active layer 77 for a channel and the source/drain regions of the TFT. The active layer 77 is connected to the polysilicon pads 75b and 75c via the openings 76a formed in the gate oxide film 76. The polysilicon film may otherwise be formed by depositing an amorphous silicon thin film by way of low pressure CVD and then annealing the thin film at a temperature of about 600.degree. C. for re-crystallization. Further, the polysilicon film may be doped with such an impurity as phosphorus or arsenic in a low dose of about 10.sup.12 cm.sup.-2 to about 10.sup.13 cm.sup.-2 by ion-implantation to adjust the threshold voltage of the TFT.
Next, as shown in FIG. 29, a resist is applied on the entire surface of the silicon substrate 70, and then patterned into a desired configuration by photolithography process to form a resist pattern 78. Using the resist pattern 78 as a mask, boron or BF.sub.2 ions are implanted into the active layer 77 in a high dose of about 10.sup.14 cm.sup.-2 to about 10.sup.15 cm.sup.-2 to form the source/drain regions 77c and 77a of the TFT. A portion of the active layer 77 covered with the resist pattern 78 is not doped with the P-type impurity, thus forming the channel 77b of the TFT.
After the resist pattern 78 is removed, a CVD oxide film 79 with a thickness of about 400 nm to about 1000 nm is deposited on the entire surface of the substrate to form an interlayer insulation film, as shown in FIG. 30.
Then, as shown in FIG. 31, an opening 79a is formed in the CVD oxide film 79 above the polysilicon pad 75c by photolithography and RIE process.
In turn, as shown in FIG. 32, the opening 79a is refilled with a metal such as Al, Cu, Ti or W, or an alloy or silicide thereof which is patterned to form a wiring 80. The wiring 80 is connected to the polysilicon pad 75c through the opening 79a formed in the CVD oxide film 79.
An interlayer film, through-holes, a second metal wiring layer and a protection film, if necessary, are formed in a known manner to complete the SRAM cell (not shown) having TFTs as PMOS load transistors.
In the SRAM cell fabricated in accordance with the aforesaid conventional process, the polysilicon pad 75c serves to prevent an adverse effect caused by an over-etching of the CVD oxide film 79 in directly connecting the wiring 80 to the source region 77c. In such a case, the CVD oxide film 79 on the thin active layer 77 has to be removed by etching, and if the selective etching ratio of the oxide film to the active layer made of polysilicon is less than about 10, for example, the active layer 77 may be broken trough by overetching. Therefore, the opening for forming the wiring 80 is formed on the relatively thick polysilicon layer 75c to prevent the breakthrough of the active layer 77. This ensures the connection between the source region 77c of the TFT and the wiring 80, while preventing the wiring 80 from contacting other wiring layers.
However, this fabrication process has such problems as stated below. In the aforesaid SRAM cell, power is supplied to the wiring 80 as a Vcc line, the polysilicon pad 75c highly doped with the N-type impurity, and the source region 77c of the TFT highly doped with the P-type impurity in the order. In other words, power is supplied in the reverse direction of a polysilicon PN junction. In general, when power is supplied in the reverse direction of the polysilicon PN junction, the rectification characteristic of the TFT becomes low. However, the low rectification characteristic was not conventionally recognized as a problem because of a relatively large junction leak current due to a low crystallization of polysilicon. In recent years, improved crystallization of polysilicon has now recognized that the major problem in the power supply to the memory cell is caused by the low rectification characteristic of the TFT. If the power supply to the memory cell is insufficient, a current supply to a storage node such as formed at a point A or B shown in FIG. 11 becomes insufficient, thereby deteriorating a stable data retention. This may result in such a serious problem as the missing of memory.
Further, a PN junction is also formed at the juncture of the drain region 77a of the TFT and the polysilicon pad 75b in the memory cell region. Since this PN junction is a forward direction junction unlike the aforesaid power supply section, there is no fear of insufficient power supply. However, the forward direction current supply requires a voltage of not less than about 1 V, because a built-in potential observed at the PN junction is about 0.9 eV or more. That is, at the early stage of the current supply with the TFT being turned on, the potential applied to the PN junction is lower than the built-in potential, hence the current supply to the storage node is restricted. Even after a sufficient time has elapsed since the TFT was turned on, the potential of the storage node is reduced by the built-in potential, and cannot be raised up to the power supply potential. This reduces the amount of electric charge stored in the storage node. Accordingly, such problems as deterioration of data retention capability and read-out errors may occur.
One approach to avoid the formation of the PN junction between the polysilicon pad 75c and the source region 77c made of polysilicon is that the polysilicon pad 75c and the source region 77c are formed of a polysilicon doped with an impurity of the same conductivity type, for example, P-type impurities such as boron is diffused into the polysilicon. In this case, however, the polysilicon pad 75b is directly connected to the N-type source/drain region 74 of the drive transistor DTr1 at the connection point of the TFT and the drive transistors DTr1 and DTr2, i.e., at the connection point between the drain region 77a and polysilicon pad 75b. That is, the P-type impurity diffuses from the polysilicon pad 75b into the N-type source/drain region 74 of the drive transistor DTr1. This will bring about such problems as an increased resistance of the source/drain region 74 of the drive transistor DTr1, a variation in the threshold voltage due to the diffusion of the P-type impurity to the channel section.
S. Ikeda et al reported a semiconductor device comprising a TFT-type SRAM which can avoid parasitic rectification characteristic of a PN junction formed by connecting a p.sup.+ source/drain region of a PMOS load TFT to an n.sup.+ wiring layer formed thereunder (see Technical Digest,IEDM, 1990, pp.469-472). In accordance with a production process described in this literature, however, the PN junction is formed at a reduced temperature (more specifically, at a temperature below the melting point of a BPSG employed as an insulation film) during the production steps after the formation of the TFT. Accordingly, the surface of the insulation film is not sufficiently planarized, and this may result in the breakage of a wiring layer.